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Renesas Electronics /R7FA6M3AH /GLCDC /SYSCNT_STCLR

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Interpret as SYSCNT_STCLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)VPOSCLR 0 (0)L1UNDFCLR 0 (0)L2UNDFCLR

L1UNDFCLR=0, L2UNDFCLR=0, VPOSCLR=0

Description

System Control Block Status Clear Register

Fields

VPOSCLR

Graphics 2 specified line detection flag clear field

0 (0): No operation

1 (1): Clears the specified line detection flag.
L1UNDFCLR

Graphics 1 underflow detection flag clear field

0 (0): No operation

1 (1): Clears the graphics 1 underflow detection flag.
L2UNDFCLR

Graphics 2 underflow detection flag clear field

0 (0): No operation

1 (1): Clears the graphics 2 underflow detection flag.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data